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Atomera Inc  (ATOM)
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Atomera Inc Segments

 
 

Business Segments III. Quarter
Revenues
(in millions $)
(Sep 30 2019)
%
(of total Revenues)
III. Quarter
Income
(in millions $)
(Sep 30 2019)
%
(Profit Margin)
Total
0.25 100 % -3.09 -

• View Income Statement • View Competition by Segment • View Annual Report

Growth rates by Segment III. Quarter
Y/Y Revenue
%
(Sep 30 2019)
Q/Q Revenue
%
III. Quarter
Y/Y Income
%
(Sep 30 2019)
Q/Q Income
%
Total
164.58 % 262.86 % - -

• View Growth rates • View Competitors Segment Growth • View Market Share

To get more information on Atomera Inc's Total segment. Select each division with the arrow.

  Atomera Inc's

Business Segments Description



For years, the semiconductor industry was able to almost double the number of transistors it could pack into a single microchip about every two years, a rate of improvement commonly known as “Moore’s Law.” The semiconductor industry uses the term “node” to describe the minimum line width or geometry on a semiconductor chip, expressed in nanometers, or nm, for today’s technologies. Historically, the smaller the node, the smaller the transistors and the more closely they are packed together, producing chips that are denser and thus less costly on a per-transistor basis. Frequently, smaller nodes also correspond to an improvement in chip performance, making them the mile markers of Moore’s Law, with each node marking a new generation of chip-manufacturing technology.

Until recently, the industry succeeded at maintaining the rate of improvement predicted by Moore’s Law by scaling the key transistor parameters, such as shrinking feature sizes and operating voltages, thereby allowing more transistors to be packed onto a single microchip. This trend was facilitated in large part by the development of the CMOS technologies. However, a discontinuity in the rate of improvement delivered by scaling appeared a few years ago when transistor technology reached feature sizes below 100 nanometers. The industry responded with advanced materials to supplement the ongoing geometry shrinks. Some of those materials advances included strained silicon, Silicon on Insulator and High-K/Metal Gate.

In addition, due to the popularity of mobile devices and other electronic products, there is increasing demand for integrated circuits and systems with greater functionality and performance, reduced size, and much less power consumption as key requirements.

The designers and manufacturers of integrated circuits and systems — our potential customers — are facing intense pressure to deliver innovative products at ever shorter times-to-market, as well as at lower prices. In other words, innovation in chip and system design today often hinges on “better, sooner and cheaper.” We believe that the semiconductor industry has accepted that moving forward in the nano-era will require adoption of new innovations that extend the scaling formula, including those based on the use of new engineered materials, a market opportunity our MST® technology seeks to address. Because shrinking geometries at the smaller nodes incurs higher capital and manufacturing costs, only limited products can take on the increased cost burden and still be economically viable. We believe cost sensitive devices will turn to engineered materials, like MST®, to solve this problem.

Vertical Disaggregation of the Industry

In trying to keep research and development costs manageable, while attempting to satisfy the demand for increasingly complex semiconductors, certain designers and manufacturers of integrated circuits have transitioned to an open innovation model in which competing companies and third-party providers actively collaborate to address performance issues through various alliances, joint ventures, and licensing of externally developed technology.

Historically, most semiconductor companies were vertically integrated. They designed, fabricated, packaged and tested their semiconductors using internally developed software design tools and manufacturing processes and equipment. As the cost and skills required for designing and manufacturing complex semiconductors have increased, the semiconductor industry has become disaggregated, with companies concentrating on one or more individual stages of the semiconductor development and production process. This disaggregation has fueled the growth of fabless semiconductor companies, design tool vendors, semiconductor equipment manufacturers, third-party semiconductor manufacturers (or foundries), semiconductor assembly, package and test companies, and intellectual property companies that develop and license technology to others.

While specialization has enabled greater development and manufacturing efficiency, it has also created an opportunity for IP-based companies, such as Atomera, that develop and license technology to meet fundamental, industry-wide challenges. These intellectual property companies have been able to gain broad adoption of their technology throughout the industry by working with companies within the semiconductor supply chain to evaluate and integrate their technology. Manufacturers and designers of semiconductors increasingly find it more cost-effective to license technologies from IP-based companies than internally developing processes that are not their core competence. Industry participants often will share a portion of the large up-front development cost of these technologies in exchange for a lower licensing fee or royalty rate. We believe this collaboration and integration benefits semiconductor companies by enabling them to bring new technology to market faster and more cost-effectively.

We do not intend to design or manufacture integrated circuits directly. Instead, we intend to develop and license technologies and processes that will offer the designers and manufacturers of integrated circuits a low-cost solution to the industry need for increased performance. Our customers and partners are expected to include foundries, integrated device manufacturers, or IDMs, fabless semiconductor manufacturers, OEMs, that manufacture epitaxial deposition, or EPI, machines, and electronic design automation software companies, such as Synopsys.

We intend to generate revenue through licensing arrangements whereby foundries and IDMs pay us a license fee for their use of MST technology in the manufacture of silicon wafers as well as a royalty for each silicon wafer or device that incorporates our MST technology. We also intend to enter into licensing arrangements with fabless semiconductor manufacturers pursuant to which we will charge them a royalty for each device they sell that incorporates our MST technology. The IDMs and fabless semiconductor manufacturers are the primary beneficiaries of our commercialization activities, as they are producers and distributors of the integrated circuits onto which we will endeavor to incorporate our MST technology. The foundries and OEMs also play an important role in our commercialization strategy in that these parties have traditionally sought to provide new technologies to their customers, which in the case of the foundries are the fabless semiconductor manufacturers and in the case of the OEMs are the IDMs and foundries that purchase EPI machines.

   

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