Amkor Technology Inc.  (AMKR)
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Amkor Technology Inc. Segments


Business Segments II. Quarter
(in millions $)
(Jun 30 2022)
(of total Revenues)
II. Quarter
(in millions $)
(Jun 30 2022)
(Profit Margin)
1,504.87 100 % 125.47 8.34 %

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Growth rates by Segment II. Quarter
Y/Y Revenue
(Jun 30 2022)
Q/Q Revenue
II. Quarter
Y/Y Income
(Jun 30 2022)
Q/Q Income
13.48 % -5.76 % 4.54 % -26.72 %

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  Amkor Technology's

Business Segments Description


Overview of Semiconductor Manufacturing Process

In general, the semiconductor manufacturing process consists of IC design, wafer fabrication, wafer probe, packaging and final test.

Integrated circuit design involves the laying out of electronic components, such as transistors, resistors, capacitors and the metallic interconnect of these components, to achieve the desired device functionality. Wafer fabrication is a multiple-step sequence of photolithographic and chemical processing steps during which the IC's are gradually created on semiconductor material, typically a silicon wafer. Individual IC's are generally known as a “chip” or “die”, and a single wafer will contain many die. Wafers are fabricated by two types of companies - IDMs which design and fabricate wafers using their own in-house manufacturing facilities, and contract foundries which manufacture wafers that are designed by fabless companies or other customers.

The packaging and test services we provide occur subsequent to wafer fabrication. The wafers that we receive from our customers are generally consigned to us; we do not own the consigned wafers or record their value in our financial statements. During wafer probe, each individual die is electrically tested, or probed, for defects. Packaging is the processing of bare die to facilitate electrical connections and heat dissipation and protect the die. The wafer is separated into individual die. Each good die is then assembled into a package that typically encapsulates the die for protection and creates the electrical connections used to connect the package to a printed circuit board, module or other part of the electronic device. In some packages, chips are attached to a substrate or leadframe carrier through wirebonding or flip chip interconnects and then encased in a protective material. Or, for a wafer-level package, the electrical interconnections are created directly on the surface of the die so that the chip may be attached directly to other parts of an electronic device without a substrate or leadframe. The packages are then tested using sophisticated equipment to ensure that each packaged chip meets its design and performance specifications.

Packaging and Test Technologies and Processes

Our packages employ wirebond, flip chip, copper clip and other interconnect technologies. We use leadframe and substrate package carriers, and we perform a variety of test services.

Interconnect Technologies

Wirebond: In packages that employ wirebond interconnect technology, the die is mounted face up on the package carrier and the interconnections between the die and package carrier are made through very fine gold, silver or copper wires which are attached from the bond pads of the die to the package carrier. The interconnections are placed along the perimeter of the die. Wirebonding is generally considered to be the most cost-effective and flexible interconnect technology and is used to assemble the majority of semiconductor packages.

Flip Chip: In packages that employ flip chip interconnect technology, the interconnections between the die and package carrier are made through conductive “bumps” that are placed directly on the die surface utilizing a process called wafer bumping. The bumped die is then “flipped over” and placed face down, with the bumps connecting directly to the package carrier. Flip chip allows a higher number of interconnects than wirebond as it uses the entire surface area of the die, and sometimes the perimeter as well, instead of just the perimeter as used by most wirebond packages. Flip chip also provides enhanced thermal and electrical performance, and enables smaller die and thinner, smaller form factors (or physical package dimensions).

The wafer bumping process consists of preparing the wafer for bumping and forming or placing the bumps. Preparation may include cleaning, removing insulating oxides and providing a pad metallurgy that will protect the interconnections while making good mechanical and electrical connection between the bump and the wafer.

Copper Clip: Copper clip interconnect technology uses a solid copper bridge or “clip” to connect the die to the package carrier. The clip allows a higher level of current flow than a wire and also provides a better method of heat transfer from the die. The clip is either spot welded, or more often re-flow soldered, to the die pads and the package carrier pads.

Package Carriers

Leadframe: A leadframe is a miniature sheet of metal, generally made of copper and silver alloys, on which a pattern of electrical connections (or “leads”) has been cut. The leads are generally placed around the perimeter of the leadframe and are used to connect the package to the system board. The number of leads on an individual leadframe is limited as electrical shorting can occur if the leads are placed too close together.

Substrate: A substrate is a laminate of either single or multiple layers of epoxy resin, woven glass fibers and metal conductors. Solder bumps provide the electrical connection to the system board. The bumps are typically distributed evenly across the bottom surface of the substrate (called a “ball grid array” format). This allows less distance between individual leads and a higher number of interconnects than leadframe packages.

Test Services

Amkor provides a complete range of semiconductor testing services including wafer testing or probe and final test. We offer a full range of test software, hardware, integration and product engineering services, and we support a range of business models and test capabilities. Substantially all of our test business is derived from testing packages that we assemble.

Wafer Test Services: Wafer test, also referred to as wafer probe, is performed after wafer fabrication or wafer bumping to screen out defective devices prior to packaging. We offer a range of wafer test coverage that can be tailored based on the cost and complexity of the die, the package and the product. These services range from coarse level screening for major defects all the way up to probing at high digital speeds and can include full radio frequency transmit and receive as well as testing at multiple temperatures. Wafer testing can also involve a range of wafer mapping and inspection operations.

Final Test Services: After the packaging process, final test is performed to ensure that the packaged device meets the customer’s requirements. Final test spans a range of rigor and complexity depending on the device and end market application. More rigorous types of final test include testing multiple times under different electrical and temperature conditions and before and after device reliability stresses, such as burn-in. In addition to electrical testing, specialized solutions are required for packages that also process non-electric stimuli.

The electrical tests are a mix of functional, structural and system-level tests depending on the customer’s requirements and cost and reliability parameters. The electrical test equipment we use includes commercially available automated test equipment, customized and proprietary system level test equipment and innovative types of low cost test equipment developed by Amkor.

Advanced Products

Our Advanced Products include flip chip chip scale packages, wafer-level packages and flip chip ball grid array packages. These package families use flip chip interconnect technology so that the die can be connected to a substrate package carrier or, in the case of wafer-level chip scale packages, directly to a printed circuit board.

Flip Chip Chip Scale Package ("FC CSP") Products: FC CSP packages are small form factor packages where the substrate size is not much larger than the die itself. The size advantage provided by chip scale packaging technologies has made FC CSP an attractive choice for a wide variety of applications that require very small form factors such as smartphones, tablets and other mobile consumer electronic devices.

Flip chip stacked chip scale packages ("FC SCSP") stack a second die on top of the original flip-chip die. The top die is typically a memory device, and wirebond interconnects are used to attach it to the substrate. FC SCSP is frequently used to stack memory on top of digital baseband and applications processors for use in mobile devices.

We continue to drive thinner package solutions for our PoP technology through the development of ultra-thin substrates and enhancing our pre-stacking and thin die handling capabilities.

We developed fine pitch copper pillar flip chip interconnect technology, which creates interconnections at finer pitches using a plating process to reduce the number of substrate layers to facilitate very thin packages. This innovative solution is also an enabling technology for package stacking with TSVs.

Flip Chip Ball Grid Array ("FC BGA") Products: FC BGA packages are large form factor substrate-based packages which are used where processing power and speed are needed, and small form factors are not required. Our FC BGA packages are assembled around state-of-the-art substrates. Utilizing multiple high density routing layers, laser drilled vias, and ultra-fine line and space metallization, FC BGA substrates have the highest routing density available. The variety of FC BGA package options allows package selection to be tailored to the specific thermal needs of the end product. We offer FC BGA packaging in a variety of product formats to fit a wide range of end application requirements, including networking, storage, computing and consumer applications.

Mainstream Products

Our Mainstream Products include leadframe packages, substrate-based wirebond packages and MEMS packages. These package families use wirebond interconnect technology to connect a die to a leadframe or substrate package carrier.

Leadframe Packages: Leadframe packages use wirebond or flip chip technology to interconnect a die to a leadframe package carrier. Leadframe packages are used in many electronic devices and remain the most practical and cost-effective solution for many low to medium pin count applications.

Traditional leadframe packages support a wide variety of device types and applications. Two of our most popular traditional leadframe package types are small outline integrated circuit and quad flat package, commonly known as “dual” and “quad” products, respectively, based upon the number of sides from which the leads extend. The traditional leadframe package family has evolved from “through hole design,” where the leads are plugged into holes on the circuit board to “surface mount design,” where the leads are soldered to the surface of the circuit board. We offer a wide range of lead counts and body sizes to satisfy variations in the size of customers’ semiconductor devices.


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