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Dry Strip

Dry strip is the removal of the masking layers from the wafer after the patterning process has been completed for that step of IC manufacturing. The objective is to eliminate the masking material from the wafer as quickly as possible, without allowing any surface materials to become damaged.

We continue to be a leader in the dry strip market. Our SUPREMA strip systems utilize an innovative wafer handling architecture to deliver low cost of ownership for IC manufacturing. The SUPREMA features our patented Faraday-Shielded inductively coupled plasma ("ICP") technology offering superior resist dry strip capability to leading edge memory and foundry/logic customers. Our product development focus has been to develop incremental enhancements to enable dry strip of advanced materials and for advanced 3-dimensional IC structures. The SUPREMA XP is the result of this development and is installed at many global semiconductor companies for production and process development of advanced 3D devices.

Etch

Etching is the process of selectively removing mask patterned materials from the wafer's surface to create desired patterns on the wafer's surface. Plasma etch is the use of a radio frequency ("RF") excited plasma to produce chemically reactive species from various gases. The reactive plasma is exposed to the wafer surface and etches away the material not protected by a masking layer.

Our plasma etch products, the paradigmE and Alpine, are built on our high-throughput platform to provide high overall equipment efficiency. Our plasma etch products feature proprietary Faraday-Shielded ICP plasma source combined with etch bias control. Our paradigmE XP etch system, with a unique dual ICP source, allows enhanced on-wafer performance to meet the increasingly stringent technology requirements for sub-20 nanometer and 3D device production. The paradigmE and Alpine systems are installed at global semiconductor companies for production and process development at advanced memory and foundry/logic wafer fabs.

Rapid Thermal Processing (conventional)

Conventional RTP refers to a semiconductor manufacturing process that heats silicon wafers to high temperatures (up to 1200°C or greater) using high intensity lamps on a timescale of several seconds or less to set the electrical properties of the semiconductor devices. RTP consists of heating a single wafer at a time in order to affect its electrical properties. The single-wafer approach allows for faster wafer processing with shorter annealing times from less than one second to three minutes, and more precise control of the annealing profile and ambient processing parameters on the wafer.

Our Helios XP product continues to run high-volume production for DRAM, NAND and foundry customers. The Helios XP is established in industry leading IC production for 20 nanometer and below based on its dual side wafer heating and differential thermal energy control ("DTEC"). The Helios XP system's temperature control architecture specifically aims at addressing advanced logic processing requirements, through its differentiated capabilities. Mattson serves major foundry/logic customers who have purchased the Helios XP beyond the 20 nanometer technology node.

Millisecond Anneal

MSA refers to a semiconductor manufacturing process that heats silicon wafers to high temperatures (up to 1200°C or greater) on a millisecond timescale of 10 milliseconds or less to set the electrical properties of the semiconductor devices. MSA consists of rapidly heating the top surface of a wafer for extremely short times in order to affect its electrical properties only near that top surface without increasing the temperature of the rest of the wafer which could cause adverse effects on the overall IC device performance.

Millios, which features a patented arc lamp technology capable of greatly reducing thermal cycle time, is designed to enable our customers to meet advanced gate anneal and activation process requirements at the 20 nanometer technology node and beyond. MSA is required for key processes in most advanced technology nodes where the high temperature exposure requires less than a tenth of a second. The capability to control anneal times in the millisecond time regime, has enabled leading foundry/logic customers to improve transistor performance in sub-20 nanometer technology nodes. The Millios system has been qualified and released for sub-20 nanometer high volume advanced foundry/logic production at multiple manufacturing sites.

   

Tax Rate Companies within the Industry


Business Segments Q1
Revenues
(in millions $)
Q1
Income
(in millions $)
(Mar 27 2016)
%
(Profit Margin)
Total 28.69 -4.00 -

Growth rates by Segment Q1
Y/Y Revenue
%
(Mar 27 2016)
Q/Q Revenue
%
Q1
Y/Y Income
%
(Mar 27 2016)
Q/Q Income
%
Total -50.75 % - - -

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